1. Field of the Invention
The present invention relates to a transmitting circuit of a portable telephone or the like as a mobile telephone and, more particularly, to a transmitting circuit of what is called a dual mode mobile telephone which is used in both of the CDMA (Code Division Multiple Access) system and the FDMA (Frequency Division Multiple Access) system.
2. Description of the Related Art
A conventional transmitting circuit comprises, as a part of the construction is illustrated in FIG. 3, a QPSK modulator 51, a voltage controlled oscillator 61, and a PLL circuit 71. The QPSK modulator 51 is used at the time of transmission in the CDMA system. An oscillation signal is supplied from the voltage controlled oscillator 61 to the QPSK modulator 51. The voltage controlled oscillator 61 is used as a frequency modulator in the FDMA system. In both of the CDMA system and the FDMA system, the oscillation frequency of the voltage controlled oscillator 61 is controlled by the PLL circuit 71.
The QPSK modulator 51 has two mixers 52 and 53 and an adder 54. One (I signal) of baseband signals as modulation signals is supplied to the mixer 52. Similarly, the other baseband signal (Q signal) as a modulation signal is supplied to the other mixer 53. An oscillation signal from the voltage controlled oscillator 61 is switched by a change-over switch 55 to either the mixers 52 and 53 or the adder 54. In this case, since the oscillation signal is supplied to the mixer 53 via a phase shifter 56, the phases of the oscillation signals supplied to the mixers 52 and 53 are different from each other at 90 degrees.
The PLL circuit 71 has a variable frequency divider 72 for dividing the frequency of the oscillation signal outputted from the voltage controlled oscillator 61, a phase comparator 73 to which the frequency-divided oscillation signal is supplied, a lowpass filter 74 for smoothing an error signal outputted from the phase comparator 73, and a reference oscillator 75 for outputting a reference signal to the phase comparator 73. A control voltage is supplied from the low pass filter 74 to the voltage controlled oscillator 61. Channel data from a communication channel setting circuit 76 is supplied to the variable frequency divider 72 and the frequency of the oscillation signal of the voltage controlled oscillator 61 is set. A voice signal A as a modulation signal is supplied to the voltage controlled oscillator 61.
When the above construction is used in the CDMA system, a modulation signal is supplied to the mixers 52 and 53 and the oscillation signal from the voltage controlled oscillator 61 is switched to the mixers 52 and 53 by the change-over switch 55. In this case, a modulation signal for frequency modulation is not supplied to the voltage controlled oscillator 61. The oscillation signal is subjected to the QPSK modulation. The resultant signal is outputted to an amplifier 57 via the adder 54, subjected to the frequency conversion by a mixer (not shown), and outputted to an antenna. The oscillation frequency of the voltage controlled oscillator 61 at this time is about 260 MHz. Since the frequency band of the baseband signal as a modulation signal is about 600 kHz, the frequency of a reference signal to be supplied to the phase comparator 73 in the PLL circuit 71 is set to 1.23 MHz which is about twice as high as 600 kHz, thereby avoiding interference with the baseband signal. The frequency dividing ratio of the variable frequency divider 72 is therefore set to approximately 217.
On the other hand, when the construction is used in the FDMA system, the baseband signal is not supplied to the mixers 52 and 53 in the QPSK modulator 51 but a modulation signal is supplied to the voltage controlled oscillator 61. The voltage controlled oscillator 61 operates as a frequency modulator in this case. Similarly, the oscillation frequency of the voltage controlled oscillator 61 is controlled by the PLL circuit 71.
Specifically, a reference signal having a frequency of 1.23 MHz from the reference oscillator 75 is supplied to the phase comparator 73 and is oscillated by the voltage controlled oscillator 61 at a frequency determined by the frequency dividing ratio of the variable frequency divider 72. A modulated signal is outputted from the voltage controlled oscillator 61 and is supplied via the change-over switch 55 to the adder 54. The adder 54 outputs the modulated signal as it is to the amplifier 57. The amplified modulated signal is similarly subjected to the frequency conversion and a resultant signal is outputted to the antenna.
In a conventional transmitting circuit, however, in order to avoid interference with the baseband signal, the frequency of the reference signal supplied to the phase comparator 73 in the PLL circuit 71 is set to a value which is about twice as high as 600 kHz that is the highest limit of the frequency components of the baseband signal. Consequently, when the voltage controlled oscillator 61 is used as a frequency modulator, that is, it is used in the FDMA system, the loop sensitivity becomes too high. As shown in FIG. 4, therefore, a problem such that a frequency deviation in the region where the frequency of the modulation signal is equal to or lower than 500 Hz abruptly decreases occurs.